In reply to verif_learner:
The most reliable way to do this is have your DUT and Testbench read parameters from a common package. You are not going to be able to change the bus width of your DUT with a run-time option.
But if you do have parameters just for your testbench, you can instantiate the test class from the top module and call run_test() with no argument, and do not provide a +UVM_TESTNAME switch.
You can also create unparameterized wrapper classes around your parameterized test class:
class test10 extends my_test#(10);
`uvm_component_utils(test10)
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
class test25 extends my_test#(25);
`uvm_component_utils(test25)
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
Now you will be able to choose between +UVM_TESTNAME=test10 and +UVM_TESTNAME=test25.