Parameterised structures/unions used as ports

SystemVerilog
,
2

In reply to alexholland:

An interface - which can be parameterized - would work, instead of a structure:

interface #( parameter WIDTH0 = 64, DEPTH0 = 512 /*other paramters*/) flags_if;
  logic [ DEPTH0 - 1 : 0 ] mode0 [ WIDTH0 - 1 : 0 ];
  //other mode flags here..
  modport driver( output mode0 /* other flags */ );
endinterface

module top;
  flags_if #( .DEPTH0( DEPTH0 ), .WIDTH0( WIDTH0 ) this_if;
  flags_submodule submod( .my_flags( this_if ) );
endmodule

module flags_submodule
(
  flags_if.driver my_flags
);

assign my_flags.mode0[ foo ] = bar;
endmodule

Classes can be parameterized too, however I’m not aware of any synthesis tool which support this for RTL code.