Parameter over-ride of array

SystemVerilog
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3

In reply to dave_59:

Thanks Dave. My mistake. What I meant was can I do the following (and this is for code that needs to be synthesized):

In the module data_array
parameter logic [(NUM_DATA-1):0][DATA_WIDTH-1):0] DATA_MASK = '{'1} // its a packed array here
In module instance
localparam logic [NUM_DATA-1:0] [DATA_WIDTH-1:0] DATA_MASK = '{32’hDEAD_BEEF, 32’hFFFF_FFFF, 32’hAAAA_AAAA};

So if I need to have all 1’s then I could say '1 and in the instance does the override have to be a list or can I just say '1. I was trying to see if the number are large like 100 then listing each would be tedious.