Parameter definition based on a case statement

SystemVerilog
1

Hi there.
I am having a problem regarding parameters. So we have some internal codegenerators that spits out a package file in system verilog. Depending on a configuration I provide in the codegenerator it will create a file like this

package my_pkg;
    function tag()
          return "tag1";
    endfunction 

    function gen_v1()
          return 1;
    endfunction

endpackage

or it will generate a file package file like

package my_pkg;
    function tag()
          return "tag2";
    endfunction 

    function gen_v2()
          return 2;
    endfunction

endpackage

The tag function will always be present.

Now in my module file I want to do something like this

case ( my_pkg::tag() )
     "tag1": localparam int param1 = my_pkg::gen_v1();
     "tag2": localparam int param1 = my_pkg::gen_v2();
endcase

// Continue using param1 as necessary

But this fails because if gen_v1 was generated by my codegenerator, it will fail on gen_v2 or viceversa. I dont know why these are getting evaluated because only one of those cases should come true.

Can anyone help me with this?

2

This is an XY Problem.

The code inside the module has to be syntactically correct for all case items as the module gets compiled. Because of potential parameterization, generate constructs get handled at a later elaboration stage.
Without knowing why do you want to do this, it’s difficult to help provide a better solution. Why can’t param1 be in the package?

3

Hi Dave.

Lol to xyproblem…but you hit the nail on its head. I do have an XY problem.

Thanks for you answer. Honestly, I wish I had a better answer than to say legacy. I totally get what you are saying though. Its just the way the codegenerator does stuff. But it looks like I need to go solve that.

Regards,
Sai.