In reply to ben@SystemVerilog.us:
Thank you, if use an automatic variable and replace join_any with join_none, your solution gives my desire output.
If use join_any, gen[1] runs after gen[0].
In reply to ben@SystemVerilog.us:
Thank you, if use an automatic variable and replace join_any with join_none, your solution gives my desire output.
If use join_any, gen[1] runs after gen[0].