In reply to fostler:
Yes I agree.
With all due respect to my colleague, that book is not the standard, nor has Janick been involved with the development of the Verilog/SystemVerilog standard. I can see that one could make that statement from simple observations. In practice, no simulator is going to randomly interleave statements without some predictable cause.
There are a few places in the LRM where order is undefined, but people have come to depend a specific implementation to give them a specific ordering of what should be a race condition.