The Forums: All Topics | Verification Academy is an interesting interactive SystemVerilog forum where users seek solutions to real application issues/problems. Many of those questions are about assertions, and SVA has very specific set of rules that do not necessarily address complex users’ requirements. This paper brings a collection of a few most interesting and challenging users’ questions and provide solutions along with explanations about getting around (or working with) SVA, or using other alternatives (see SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy). It turns out that many of these solutions require a different point of view in approaching the assertions, and often require supporting logic. All code along with simple testbenches is provided.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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