Packed array declaration

SystemVerilog
1

NoApbSlaves=34
AXI_DATA_WIDTH=512

1st way

 input data_t [NoApbSlaves-1:0] prdata_i;

Here data_t = logic [AXI_DATA_WIDTH-1:0]
therefore this will expand to

input  logic [AXI_DATA_WIDTH-1:0] [NoApbSlaves-1:0] prdata_i;

2nd way:

input logic [NoApbSlaves-1:0] [AXI_DATA_WIDTH-1:0] prdata_i;

The signal i see in waveform is same after trying both types of declaration. Meaning the signal is seen as [33:0][511:0] prdata_i. I believe this should happen only with 2nd way of declaration.

Am i missing some understanding here?

How come first way of declaration is correct?

2

It would really help to put this into an example we can try without waveforms.

This works as expected for me

module top;
  
  parameter NoApbSlaves=4,AXI_DATA_WIDTH=8;
  typedef logic [AXI_DATA_WIDTH-1:0]data_t;
  data_t [NoApbSlaves-1:0] data_typed;
  logic [AXI_DATA_WIDTH-1:0] [NoApbSlaves-1:0] data_1stway;
  logic [NoApbSlaves-1:0] [AXI_DATA_WIDTH-1:0] data_2ndway;
  
  int r = $urandom;
  initial begin
    data_typed = r;
    data_1stway = r;
    data_2ndway = r;
    $displayb("%p", data_typed);
    $displayb("%p", data_1stway);
    $displayb("%p", data_2ndway);
  end
endmodule

# '{01100101, 11001111, 11001101, 00100110}
# '{0110, 0101, 1100, 1111, 1100, 1101, 0010, 0110}
# '{01100101, 11001111, 11001101, 00100110}
1 Like
3

Thanks a ton for the response and example.
Yes. This is what i expected but my 1st ( input data_t [NoApbSlaves-1:0] prdata_i;) and 2nd (input logic [NoApbSlaves-1:0] [AXI_DATA_WIDTH-1:0] prdata_i;) are same.
Let me check.