Package export does not work like I expect

SystemVerilog
4

In reply to dave_59:

Dave,
We had a similar requirement when trying to wrap UVM pkg into our own, custom package. Do you think it is reasonable to ask for an extension in the language for it? Consider:

package our_uvm_pkg;
import uvm_pkg::all; // Just a notion, for now it won’t work
export uvm_pkg::all; // Just a notion, for now it won’t work
// More code, uses some of the uvm base classes, but not all
endpackage : our_uvm_pkg

The benefit is user then has to import only “our_uvm_pkg” and gets all what’s provided by UVM.

Thanks
Srini
http://www.verifworks.com