I have a derived_sequencer which extends from uvm_sequencer, and has one additional property - vif as follows.
class derived_sequencer extend uvm_sequencer;
…
virtual interface vif;
…
endclass
Then inside my sequence, I use below macro to (as UVM says) 1) declare p_sequencer of derived_sequencer type and 2) cast m_sequencer to p_sequencer.
class my_sequence extends uvm_sequence;
…
`uvm_declare_p_sequencer(derived_sequencer)
…
endclass
As a result, I can use p_sequencer to access vif which is member of derived_sequencer but NOT in uvm_sequencer.
However, the WEIRD thing now is that now I can use m_sequencer to access vif as well ?! What I thought was only p_sequencer could do the access to vif.
Why is this happening ? In systemverilog the “$cast (dest, source)” would not change the source type.
Regards,
David