In reply to mperyer:
This is a basic principal of inheritance and polymorphism.
m_sequencer is variable of type uvm_sequencer. It can store a handle to any object derived from uvm_sequencer. But you can only reference methods or variables from uvm_sequencer, or any of the classes that uvm_sequencer was extended from.
Lets say you have two classes extended from uvm_sequencer: sqrA and sqrB sqrA has a member A and sqrB has a member B. What would happen if you tried to reference m_sequencer.A, but m_sequencer currently has a handle to an object of type sqrB? Also, what if sqrA and sqB both had variables called C but they were completely different types? SystemVerilog does not let you make this mistake, not does it allow dynamic type switching.
So if you want to reference members or methods that are only in sqrA, you have to reference them with a variable of that class type. It knows that sqrA_h.A is always valid if sqrA_h is not null, and that sqrA_h.M is a fixed type.