Overwriting Assign statement

UVM
3 

  interface ALU_in_if; 
  logic clk;
  logic rst;
  logic[2:0] temp;
endinterface


module UVM_Top;
  ALU_in_if my_ALU_in_if();
  assign #5 my_ALU_in_if.temp = my_ALU_in_if.temp + 1; //the assign statement
  initial begin
  end
endmodule

//In UVM driver 
virtual ALU_in_if mydriver_ALU_in_if;
uvm_config_db#(virtual ALU_in_if)::get(this,"","ALU_in_vif",mydriver_ALU_in_if)
task run_phase(uvm_phase phase);
  super.run_phase(phase);
  mydriver_ALU_in_if.temp = 5; //overwriting the assign statement
  $display("TEMP = %0d",mydriver_ALU_in_if.temp); 
endtask

How is it possible to overwrite the assign statement inside a procedural code?