Overriding imported module parameters

SystemVerilog
2

In reply to Adam Krolnik:

Importing a package into a scope just makes the identifiers in the package visible to that scope; it does not move the deffiniton of the identifier (in your case a parameter) into that scope.
And if you want to have multiple instances of the module nest with different parameter values, you need to declare the parameters separately in the module.

module nest ;
  import axi4_pkg::*;
  parameter XD = axi4_pkg::XD;
  parameter MM = 2;            
 

  initial $display("%m: XD is %0d.", XD);  // prints "XD is 64."
  initial $display("%m: MM is %0d.", MM);  // prints "MM is 4."
endmodule

Now parameter XD can be overridden per instance but shares a common default value from the package.