Overlapping and Non-Overlapping Implication code

SystemVerilog
, ,
2

Yes, you’re right!

This:


property rule_2;
@(posedge clk)
$rose(start) |=> ##2 $rose(transfer);
endproperty

Is equal to this:


property rule_2;
@(posedge clk)
$rose(start) |-> ##3 $rose(transfer);
endproperty