Out of order in driver and scoreboard

UVM
, ,
7

In reply to UVM_beginner:

WRT to 1) I do not really understand what you mean. On the driving side there is always a one-to-one connection, 1 sequencer connected to 1 driver.
WRT to 2): here is a piece of codewith the fundamentals:

forever
begin
  seq_item_port.get(requ[i++]);

  @(posedge dut_vi.clock);
  dut_vi.cmd <= requ[i].cmd;
  ...
  fork
    begin
      my_tx resp;
      resp = my_tx::type_id::create("resp");
      resp.data = dut_vi.data;
      resp.set_id_info(requ[j++]);

      repeat(2) @(posedge dut_vi.clock);

      seq_item_port.put(resp);
    end
  join_none
end