OR Construct basics in Concurrent Assertions

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben ,

Along with your paper I went through the following ::

(1) SNUG09 paper "If Chained Implications in Properties Weren’t So Hard, They’d be Easy " by Don Mills

(2) VA_LINK1

(3) VA_LINK2

I have a better understanding of the Question I posted at the top and understand the O/P

However if I do a slight modification to the Sequence Expression .


sequence  ant_seq ;

 //   Attached  a  Subroutine  within  an  expression  in  a  ' sequence '  
 
 (  (  a[ *1:2 ]  ##1  b  ) , $display(" TIME : %0t  Antecedent  is  True " , $time ) ) ; 

  endsequence

[ Q ] When does the $display() execute ?

    **How  do  I  expand  the  above  expression  ::**

    Would  it  be  interpreted  as  ::


 (    ( a  ##1  b  )      ,  $display(" TIME : %0t  Antecedent  is  True " , $time ) )   or

 ( ( a  ##1  a  ##1  b  ) ,  $display(" TIME : %0t  Antecedent  is  True " , $time ) )

I have the code :: EDA_LINK2

Why do I observe 2 displays at TIME : 400 ?

Thread1 has Non - Vacuous Pass so I understand the attempt at TIME : 300 is a success . However I don’t get the 2nd $display() .