One Hot encoding

SystemVerilog
7

In reply to dave_59:

I know this is old, but I’m trying to get this to work. I’m checking my vendor for support also, but quick question:

I’ve modified the above so that ‘onehots’ holds the typical wildcard/walking 1’s pattern (e.g., ???1, ??1?, ?1??, 1???, which is so ugly for anything wide)

So the loop in new could become:

foreach (onehots[i]) begin
  onehots[i] = { WIDTH { 1'bx }};
  onehots[i][i] = 1'b1;
end

Then I made ‘bins’ be ‘wildcard bins’. It compiles, but no coverage is generated. Again, I’m checking vendor… but question is:

should this work with ‘wildcard bins’ and what I’ve shown?

Thanks!