Once a certain sequence occurs that another seq shouldn't occur till simulation ends

In reply to Srini @ CVCblr.com:

In the latter example I had added an explicit clocking event to ‘seq2’ to use .triggered.
But thanks for the interesting question, does default clocking apply to sequences (with no explicit clocks) methods ?

Here is what I found in the LRM


LRM 16.13.6 Sequence Methods ::
The sequence on which a method is applied shall either be clocked or infer the clock from the context where it is used. 
The same rules are used to infer the clocking event as specified in 16.9.3 for sampled value functions.

LRM 16.9.3 Sampled value functions ::
If called in an assertion, sequence, or property, the appropriate clocking event as determined by clock flow rules (see 16.13.3) is used.

As per LRM 16.13.3 Clock flow, sequence seq2 (with no clocking event) infers the clock from clocking event in property ‘ab’ . 2 tools agree with this


 // LRM 16.13.6  further provides an example
 default clocking cb @(posedge clk_d); endclocking
 sequence e4;
  $rose(b) ##1 c;
 endsequence
 // e4 infers posedge clk_a as per clock flow rules
 a1: assert property (@(posedge clk_a) a |=> e4.triggered);

 // Illegal use in a disable condition, e4 is not explicitly clocked
 a5_illegal: assert property( @(posedge clk_a) disable iff (e4.triggered) a |=> b );

 // Note :: 'e4.triggered' doesn't inherit the clock from default clocking !!

However LRM 16.13.3 Clock flow doesn’t mention about default clocking.

Whereas LRM 16.9.3 mentions :

Otherwise, if called outside an assertion, default clocking (see 14.12) is used.

does default clocking apply to sequences (with no explicit clocks) methods ?

Still looking for a definitive answer, any comments/suggestions from forum moderators are welcome