On the Fly reset in Testbench

UVM
,
2

In reply to rag123:

Your problem is in the driver code. See here:

  @(posedge vif.rst_n);
     forever begin
       if (!vif.rst_n) begin      
         vif.pwdata <=0;
         vif.paddr <= 0;
         vif.pwrite <=0;
       //  vif.hsize <= 0;
       //  vif.htrans <= 0;
         vif.psel <=0;
         vif.pstrb <=0;
         `uvm_info ("driver","Entering here",UVM_NONE);
         if(tr != null) begin
 tr.status = UVM_TLM_INCOMPLETE_RESPONSE;
 seq_item_port.item_done();

I see 2 problems here:
(1) You are synchronizing on the rising edbe of rst_n (reset comes out of reset). And you are continuing by checking if vif.rst_n is low

if (!vif.rst_n) begin

This should not happen, because after the rising edge of rst_n the signal is high.
(2) In this reset branch you are doing a

seq_item_port.item_done();

without a

seq_item_port.get_next_item(..);

This is reported by your simulator.