No time pass after @xxx_cb;

UVM
, ,
7

In reply to dave_59:

Thank you for your answer, but when I only use clocking block as the event control, the there still race conditions, below is my simple test:


interface my_intf(input bit sys_clk);
	clocking cb @(posedge sys_clk);
	endclocking
endinterface

import uvm_pkg::*;
module top();

bit	clk=0;
my_intf	my_intf0(clk);

initial begin
	$timeformat(-9, 1, "ns", 10);
end

initial begin
	clk = 1;
	forever begin
		#5ns	clk = ~clk;
	end
end


initial begin
	`uvm_info("", $sformatf("before"), UVM_LOW);
	@my_intf0.cb;
	`uvm_info("", $sformatf("middle"), UVM_LOW);
	@my_intf0.cb;
	`uvm_info("", $sformatf("after"), UVM_LOW);
end
endmodule

the output is printed as below:


UVM_INFO ./test.sv(1298) @ 0.0ns: reporter [] before
UVM_INFO ./test.sv(1300) @ 0.0ns: reporter [] middle
UVM_INFO ./test.sv(1302) @ 10.0ns: reporter [] after

there is no time pass between “before” and “after”.
Can you help me? please. thank you