No time pass after @xxx_cb;

[chr_sue]

In reply to dave_59:

It Looks really like a Problem with mixing CB and clk Control.
See my example below (without a CB). It works fine.

module top;

 import uvm_pkg::*;
 `include "uvm_macros.svh"

 logic clk = 1'b0;

 always #10 clk = ~clk;

 initial begin
   `uvm_info("ID0", "info1", UVM_LOW);
    @clk;
   `uvm_info("ID0", "info2", UVM_LOW);
   $stop;
 end

endmodule