In reply to UVM_LOVE:
Your testbench approach needs strong reconsiderations.
I suggest that you read my reply to this question:
Got this question:
Q: I need your advice in getting started with verification with systemverilog. I 've built various projects using Verilog and they was FPGA and ASIC synthesizable. what I need now is a road map that get me started with verification for example SVA , UVM and SV testbenches
A: To better respond to this question I am attaching a file that addresses the build of a verification plan, quick-and dirty partition testing, a reference to my co-author Srinivasan Venkataramanan on UVM, SVA and learning SVA.
I welcome comments from this community.
FIle also at LinkedIn
That link is a pdf file.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog