In reply to SparkyNZ:
I think you need to go and review a basic Verilog and SystemVerilog tutorial, what you have is a mix of continuous and non-continuous assignment (as the tool points out), I’m assuming the port Tick of your module UART_BaudRate_generator is an output assigned using the ‘assign’ keyword which is a continous assignment (occurs every time an event is evaluated, i.e input values changing), so this clashes with your initialisation in the code shown which is a procedural assignment, also keep in mind you are describing hardware and several things occur concurrently, in your case if this port is an output why would you like to initialise it outside of the module who is responsible of generating it?
The LRM https://ieeexplore.ieee.org/document/8299595 section 6.5 states the following:
“…An assignment where the left-hand side contains a slice is treated as a single assignment to the entire slice.
Thus, a structure or array can have one element assigned procedurally and another element assigned
continuously. And elements of a structure or array can be assigned with multiple continuous assignments,
provided that each element is covered by no more than a single continuous assignment…”
Regarding to the main() and initial part, initial blocks are threads that start execution at time 0, I’d suggest to go thru a tutorial (VLSI Design - Verilog Introduction | Tutorialspoint) always refer to the LRM keeping in mind that not all tool vendors support the latest version in all their tool versions, but for that you need to contact your vendor directly.
Anyways I hope this helps.and probably someone will give a more concise answer.
-R