In reply to SparkyNZ:
BTW, when asking questions, it always helps when you explain the correct value you expect versus what you were actually seeing.
I’m guessing you are seeing a 0 result, because BaudRate is still 0 at the time the initial block gets executed. That’s because you have a race condition between the initial block and the propagation of the input port. If you don’t expect BaudRate to change at any time, then you probably should declare it as a parameter instead of an input port.
module UART_BaudRate_generator #(longint BaudRate) (
input Clk , // Clock input
output bit Tick // Each "BaudRate" pulses we create a tick pulse
);
localparam longint freqFPGA = 50000000; // 50MHz;
localparam longint BaudRateClocks = freqFPGA/BaudRate; // Number of FPGA clock cycles requires for 1 baud period
longint currClockCount; // Register used to count
initial
begin
Tick = 0;
currClockCount = 0;
end
always @(posedge Clk)
begin
currClockCount ++;
if(currClockCount >= BaudRateClocks)
begin
Tick = ! Tick;
currClockCount = 0;
end
else
begin
currClockCount ++;
end
end
endmodule
parameter longint baudRate = 9600;
UART_BaudRate_generator #(.BaudRate(baudRate))
BaudGen1(
.Clk( clk ),
.Tick( baudTick )
);