Need to Use Variable in Assertions ## Delay

SystemVerilog
46

I am using the above solution to pass a variable latency to a property and perform checks, while trying to assert the property the tool is reporting “ERROR (EOBS012): Assert with local variable assignment in non supported position: Non negative environment.”

property perform_check(a,b,delay)
int v;
@(posedge clk) disable iff (rst)
( a , v = delay+1’b1 ) |-> (v>0, v= v-1’b1) [*0:$] ##1 v == 0 ##0 b )
endproperty

function int latency_check(a)

if ( a == some_expression )
latency_check = 3;
else
latency_check = 4

endfucntion

genvar i;
int latency
for(); begin
latency = latency_check(a);
perform_check_1 : assert property (perform_check(a,b,latency));
end

any solution to the above issue ?