In reply to ben@SystemVerilog.us:
hi,
I have used your above suggested code to delay using particular variable, but i am facing an issue like my assertion is getting active second time immediately where I’m not expecting and remain in active state only. Please find below code . Thanks in advance.
property to_dly_p7;
int count_p7;
@(posedge clk32r20 )
disable iff (!rst32kn)
((apcState == LD_PLL_DLY), count_p7=(reg_t_pll_delay*10)+1’b1) |=> (1, count_p7=count_p7-1’b1)[*0:$] ##1 count_p7==0 ##1 ((apcState == LD_TO_DLY) and op_signals_to_dly_p7);
endproperty
assert property ( to_dly_p7 );
The above assertion is getting active (apcState == LD_TO_DLY) at this state not remain in active.