In reply to ben@SystemVerilog.us:
(rose(a), v=delay+1'b1) |-> (v>0, v=v-1'b1)[*0:] ##1 v==0 ##0 $rose(b);
I want to check b rose 6 cycle after a raises, and during 6 cycle b should be zero, should not toggle.
Please help me to implement this in assertion.