Hello SVA Learners, I have below requirement and chose to check this scenario with the help of property writing: [image] My Requirement is as below: Referring Image posted above: Antecedent must be Sig1. When Ever sig1 asserted, I have to load the the content of register to local data_load av…

Check1: Once after sig1 asserted If data_load is changed before sig2 asserts then If sig3 is not asserted.Assertion pass condition. [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. …