Need help in writing assertion where descendent overlaps multiple precedent

SystemVerilog
1

There is 1-bit input called valid along with a clk. There is also 1-bit grant. Now implement a assertion which will monitor this valid and grant in such a way that after every rise of valid , task must see and make sure grant is received within 15 clocks, else it must through error. Remember that
Multiple valids will receive multiple grants at different time intervals , but in same order the valids were recieved

2

You will need some extra logic that counts the number of valid and grant edges, but this should get you started

property vg;
    int count;
    @(posedge clk)  
     ($rose(valid), count = valid_count) |-> ##[1:15] $rose(grant) && count == grant_count;
endproperty
3

Thanks @dave_59 for the solution. This will help.