Prior to SV 1800-2012, abstract classes served two purposes:
- A partially implemented class - Abstract classes act as expressions of general concepts from which more specific classes can be extended. An abstract class defines some default functionality with virtual methods, and requires you to add additional functionality with pure virtual methods (method prototypes with no implementation). Although the language does not require having a pure virtual method in your abstract class, there is usually no point in using the abstract class without extending it and providing some virtual method overrides. You cannot create an object of an abstract class type; however, you can reference extended objects from an abstract class typed variable. You are using polymorphism to access the virtual method in the extended class, and those virtual methods will access members of the extended class.
- An interface class containing only pure virtual methods - a completely unimplemented class. This is a way for one class to communicate with another class through a published API that is made up of the pure virtual method prototypes. That one class just needs to contain an abstract class variable to reference the other implemented object. Since SystemVerilog only allows for single inheritance, this also serves to keep the inheritance hierarchies of the two classes separate.
The difference between these two contrivances is a matter of degree in implementation inside the base class. However, SystemVerilog 2012 has formalized the concept of interface classes in a way that allows for multiple inheritance of interface classes. These are all concepts borrowed from Java, so you can search for more information in that domain.