In reply to ragnomore:
I’ve rarely seen static tasks used in SystemVerilog, just static functions. The static class member qualifier means the variable or method is specific to the type, not a particular object. Typically you use a static method to access static variables that are local or protected from access outside the class.
I do explain this further in my SystemVerilog OOP course.
You can use static methods to create parameterized versions of tasks and functions without ever constructing an object of the class. Some tools will even synthesize these.