NBA assignment of $random

SystemVerilog
, ,
2

In reply to nachumk:

There is no difference in calling $urandom in a procedural loop versus serially calling $urandom multiple times. Your code gives the desired results in several tools, including Cadence’s on EDAPlayground.com. Perhaps you are not showing is part of your problem. It always helps to show an MCVE, like

module top;
  int tmp [2] [8];
  bit clk;

  initial begin
    #1 clk=1;

    #1 $display("%p",
                tmp[0]);
  end

always @ (posedge clk) begin
    foreach (tmp[,i]) begin
        tmp[0][i] <= $urandom();
    end
end

endmodule