In reply to S.P.Rajkumar.V:
Hi,
Firstly, thank you for your fast comment on this.
Unfortunately this was a module/IP level VE. Although it has many interfaces, I still think that one layer of virtual sequence would have worked perfectly. My guess is that this implementation is a result of misunderstanding the concept UVM.
I see your point of having multiple leayers of virtual sequences when an SoC VE is together reusing the module level ones. Is there any guideline or suggestion by UVM how the connection between the layers should be established?
Regards,
Peter