Multiple $monitor system task execution

SystemVerilog
2

$monitor only uses the last invocation - it is a very primitive form of output that should only be used for the simplest debugging. It was actually designed for use before tools had waveform displays.

You could replace your initial blocks with

always_comb begin : INI_2
    $display($time,":: INI_2 | SIG_1 = %0b ::",sig_1);
  end : INI_2

BTW, a couple of comments about your clock generators.

  • You should be using 2-state bit types instead of reg types for variables that will be driven into your test
  • Always use blocking assignments except when assigning variables triggered by a clock edge.
  • Don;t use fork/join_none unless you really need it - it is usually more expensive to simulate.