Hi,
at least for the “child-grandchild” error I have a solution.
However this is just as good as a complete duplication of the register model.
How can I make the predictor understand that the registers in the two maps refer to the same DUT registers?
class my_reg_block extends uvm_reg_block;
`uvm_object_utils(my_reg_block )
rand my_reg1_rc my_reg1;
rand my_reg2_rc my_reg2;
uvm_reg_map my_regs_map_for_vme; // Block map
uvm_reg_map my_regs_map_for_jtag; // Block map
function new(string name = "my_reg_block ");
super.new(name, UVM_NO_COVERAGE);
endfunction
virtual function void build();
...
my_regs_map_for_vme= create_map("my_regs_map_for_vme", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
my_regs_map_for_vme.add_reg(my_reg1, 32'h8000 , "RW");
my_regs_map_for_vme.add_reg(my_reg2, 32'h8001 , "RW");
my_regs_map_for_jtag= create_map("my_regs_map_for_jtag", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
my_regs_map_for_jtag.add_reg(my_reg1, 32'h8000 , "RW");
my_regs_map_for_jtag.add_reg(my_reg2, 32'h8001 , "RW");
endclass
class my_register_model extends uvm_reg_block;
`uvm_object_utils(my_register_model )
function new(string name = "my_register_model ");
super.new(name);
endfunction
rand my_reg_block my_regs;
uvm_reg_map jtag_map;
uvm_reg_map vme_map;
function void build();
// default map : jtag bus sequencer
jtag_map = new("jtag_map");
jtag_map = create_map("jtag_map", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
// same map again --> attach to VME sequencer
vme_map = new("vme_map");
vme_map = create_map("vme_map", 'h0, 4, UVM_LITTLE_ENDIAN, .byte_addressing(0));
...
// add all register blocks (identical configuration) to the jtag and vme maps
jtag_map.add_submap(this.my_regs.my_regs_map_for_jtag, 'h0);
vme_map.add_submap(this.my_regs.my_regs_map_for_vme, 'h0);
// define default submap == JTAG
default_map = jtag_map;
this.lock_model();
endfunction
endclass