Hello,
I’m having trouble understanding how multi-clocking works. Could you also explain what a delta cycle is in a simulator and how can i see it using questasim or EDAPLAYGROUND?
For example , how should the simulator handle this assertion?
property my_clocks;
@(posedge clk1) S1 |=> @(posedge clk2) S2;
endproperty
also what if i have large sequences of small sequences and each one works on it’s own clock is it same as property too or different?
This topic seems complex to me. Is it possible to verify Clock Domain Crossing (CDC) using SystemVerilog Assertions?
Multi-clock and delta cycles are related but distinct topics. Multi-clock refers to a part of the design dependent on more than one clock with a different frequency or phase shift (there is a time difference between the edges of the different clocks.
Delta cycles are simulation artifact of the event scheduler when different event regions execute multiple times in the same time slot. A design with a single clock can still have delta cycles due to combinational feedback loops and gated clocks. EDAPlayground cannot show you delta cycles because the file it stores the waveforms in (VCD) does not support it.
Some CDC checks can be made using assertions. Check this paper and its references. https://lcdm-eng.com/papers/DVCon%202015%20Assertions%20for%20CDC_Final.pdf
Thank you for your reply; I really appreciate it. Could you please explain the multi-clock aspect of the property and how the simulation should handle it?
It is similar to @(posedge clk1) S1 ##1 @(posedge clk2) S2;
See SVA with multiple clocks