Most efficient way to randomize payload and length?

SystemVerilog
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4

In reply to cgales:

A slightly more efficient example:

class payload;
	rand int unsigned data [];   // dynamic array 
	constraint data_size { data.size() inside {[0:1024]}; } 
	constraint data_elem { foreach (data[ii]) data[ii] < ii; } // constraint on each element
endclass

BTW, never ever use $random in a SystemVerilog testbench; use $urandom instead. This gives you stability and command line control over seeding.