Hi,
I was referring to sva-package-dynamic-and-range-delays-and-repeats and was trying out an alternative via SV task which would provide me the flexibility of SV constructs.
The intention is to check for sequence : ( a ##1 b ) ##[min:max] ( c ##1 d ) // min and max are run-time variables with values 4 and 6 respectively.
Here is my attempt : edalink.
Ideally sequence (c ##1 d) should be checked thrice and the assertion should pass at the 1st match. It should fail only when sequence doesn’t match even after 6 clocks.
[Q1] Any suggestions ?
[2] I was referring to sequence ‘dynamic_delay’ from the package
sequence dynamic_delay(count);
int v;
(count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
endsequence
Consider a case where we call sequence as **dynamic_delay(0)**
LHS sequence: (count<=0) is a match on the very 1st clock.
In RHS sequence: ((1, v=count) ##0 (v>0, v=v-1)[*0:$] ##1 v<=0), due to empty sequence (v>0, v=v-1)[*0]
**[Q2]For the RHS shouldn't the equivalent expression ((1, v=count) ##0 v<=0) match ?**
**i.e won't both LHS and RHS sequence of the 'or' operator match on the very 1st clock ?**
I added some $display() for debugging in [edalink2](https://www.edaplayground.com/x/n4Af), but I don't observe the message "RHS Sequence matches" at T:5