Modeling dynamic delay range via subroutine

SystemVerilog
,
1

Hi,
I was referring to sva-package-dynamic-and-range-delays-and-repeats and was trying out an alternative via SV task which would provide me the flexibility of SV constructs.

The intention is to check for sequence : ( a ##1 b ) ##[min:max] ( c ##1 d ) // min and max are run-time variables with values 4 and 6 respectively.

Here is my attempt : edalink.

Ideally sequence (c ##1 d) should be checked thrice and the assertion should pass at the 1st match. It should fail only when sequence doesn’t match even after 6 clocks.

[Q1] Any suggestions ?

[2] I was referring to sequence ‘dynamic_delay’ from the package


      sequence dynamic_delay(count);
      int v;
       (count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
      endsequence
     

Consider a case where we call sequence as **dynamic_delay(0)**

LHS sequence: (count<=0) is a match on the very 1st clock.

In RHS sequence: ((1, v=count) ##0 (v>0, v=v-1)[*0:$] ##1 v<=0), due to empty sequence (v>0, v=v-1)[*0] 

**[Q2]For the RHS shouldn't the equivalent expression ((1, v=count) ##0 v<=0) match ?**

 **i.e won't both LHS and RHS sequence of the 'or' operator match on the very 1st clock ?**

 I added some $display() for debugging in [edalink2](https://www.edaplayground.com/x/n4Af), but I don't observe the message "RHS Sequence matches" at T:5
2

In reply to MICRO_91:

The intention is to check for sequence : ( a ##1 b ) ##[min:max] ( c ##1 d )

I address this with examples is my paper

http://systemverilog.us/vf/ap_a2bnext3cnextd_range.sv
ap_a2bnext3cnextd_range : assert property(@(posedge clk) $rose(a) ##2 b|-> ##[1:3] c ##1 d);

also in http://systemverilog.us/vf/a_range_one.sv
ap_a1to5b_then_3c : assert property(@(posedge clk) $rose(a) ##[1:5] b |-> ##3 c);

Regarding your code in

@( posedge clk ) a ##1 b |-> ##0( 1, dynamic_delay_range( min , max ) ) ;
Delays or wait statements in match item task calls are not supported by some tools.
This is most likely because the tool vendor implemented the task call in the Observed region rather than the Reactive region.
In any case, your task dynamic_delay_range does not consider the sequence that follows it.

On your Q2, you are correct.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog

3

In reply to ben@SystemVerilog.us:

For [Q2] I tried changing sequence ‘dynamic_delay’ with only RHS sequence :


sequence dynamic_delay(count); // Actual argument is 0
   int v;
   ( (1, v=count,$display("T:%0t v=count",$time) ) ##0 (v>0,v=v-1)[*0:$] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time)) );
 endsequence

The assertion fails at T:5 : edalink3 due to ( v>0 ) being false.

On changing the code to :


sequence dynamic_delay(count);
   int v;
   ( (1, v=count,$display("T:%0t v=count",$time) ) ##0 first_match( (v>0, v=v-1) [*0:$] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time)) ) );
 endsequence

Now I do observe “T:5 RHS Sequence matches” when calling dynamic_delay(0)

However in the original code ( edalink2 ) since the expression within dynamic_delay(0) is equivalent to:


 (count<=0) or ( ( (1,v=count) ##0 (v>0, v=v-1)[*0] ##1 (v<=0) ) or ( (1,v=count) ##0 (v>0, v=v-1)[*1] ##1 (v<=0) ) or ... ( (1,v=count) ##0 (v>0, v=v-1)[*N] ##1 (v<=0) ) )

LHS sequence : ( count<=0) is a match at T:5

RHS sequence consists of multiple sequences 'or’ed : ( seq1 or seq2 or … seqn )


( (1,v=count) ##0 (v>0, v=v-1)[*0] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time) ) ) or  // seq1
( (1,v=count) ##0 (v>0, v=v-1)[*1] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time) ) ) or  // seq2
............................................................................................  or
( (1,v=count) ##0 (v>0, v=v-1)[*N] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time) ) )

seq1 has a empty sequence ( (v>0, v=v-1)*[0] ) due to which it can re-written as : (1,v=count) ##0 (v<=0,$display(“T:%0t RHS Sequence matches”,$time))

So why is it that RHS sequence isn’t considered a match at T:5 ? ( since I don’t observe “T:5 RHS Sequence matches” for edalink2 )

Since the input argument ‘count’ is 0, the sequence (v>0) fails for ALL sub-sequences of the RHS sequence i.e essentially RHS sequence ends at T:5.
As per my understanding sub-sequence seq1 does match at T:5, however there is no message “T:5 RHS Sequence matches” in output :(
Am I missing something ?

4

In reply to MICRO_91:
Your analysis of (count<=0) or … not being needed is correct.
This seems to be a tool issue and I’ll be addressing this with the vendors.
Curiously, adding () gives different results.
dynamic_delay( 0 ) using RHS sequence(1) - EDA Playground // code
Since we don’t address tools, I can’t go further on this.
In my dynamic_delay(count) sequence I originally added the **(count<=0) or …**to make the code work and bypass any tool issue.
Reality of life!
:)
Ben

5

Using left to right associativity ‘seq1’ is a No match ( 0 ) due to (1,v=count) ##0 (v>0, v=v-1)[*0]
The rest of the sequence ##1 (v<=0,$display(“T:%0t RHS Sequence matches”,$time) ) is never evaluated.

Hence your display message “T:5 RHS Sequence matches” doesn’t execute.

As Ben suggested by adding an enclosed parenthesis in your RHS sequence

( (1, v=count) ##0 ( (v>0, v=v-1) [*0:$] ##1 (v<=0,$display("T:%0t RHS Sequence matches",$time)) ) );
//                 ==                                                                           ==

In this case your ‘seq1’ is equivalent to :: (1,v=count) ##0 (v<=0,$display(“T:%0t RHS Sequence matches”,$time) )
Hence the display message “T:5 RHS Sequence matches” executes.

6

Ben ,

  1. I believe the tools are correct in their output.
    By simply adding an enclosed parenthesis your sequence ‘dynamic_delay’ from sva-package-for-dynamic-and-range-delays-and-repeats can be re-written as
// ******       DYNAMIC DELAY ##d1 **********
    // Implements     ##[d1] 
    // Application: sq_1 ##0 dynamic_delay(d1) ##0 sq_2;
    sequence dynamic_delay(count);
        int v;
     ( (1, v=count) ##0 ( (v>0, v=v-1) [*0:$] ##1 v<=0 ) );
    endsequence // dynamic_delay

When actual to count is 0 / -ve value sequence is equivalent to

( (1, v=count) ##0 v<=0 ) )

It matches at the same time that the sequence is invoked

  1. Using dynamic_delay(0) ,
    Why is it that we observe either “T:5 LHS Sequence matches” or “T:5 RHS Sequence matches” ?
    ( 3 tools shows one of the either message but not both , 1 tool shows both messages )
    Since both LHS and RHS sequence match at T:5 , shouldn’t we observe both messages ?
    Or is it that due to implicit first_match in consequent that a tool shows only one message ?
    Ideally as per LRM would it be incorrect if a tool were to show both display messages ?