Modeling a pipeline

I think I figured out why this happens. The individual pipeline stages tasks (fetch_process, decode_process, etc) do not have any delay. So basically the queue at the end of the fetch_process are updated in the same cycle as when the decode process starts. The decode process is waiting for decode_instr_q to be not-zero and seems to get processed in the same cycle.

Can someone tell me how to get around this in SV?