Mismatch between read and mirrored value

In reply to chr_sue:

Hi ,

Could you elaborate ?

The chain of events is as follows ::

(1) I have ctrl register at address 0x40 . If this is high ( write(status,1) ) then the register will shift

(2) I have a shift register ( Actually a LFSR ) at address 0x44 . the value written into it acts as initial seed . Since ctrl_reg is high ( due to write(1) at address 0x40 previously ) for successive clocks it shifts data ( the seed written into it ) based on some polynomial .
The write occurs at address 0x44 , so does the read .

Thanks