Mirroring in Register Abstraction Layer

UVM
6

I know this question has been answered. but i have a few questions about mirroring. I hope you will be able to clear those.

  1. Why do we require a mirror variable and a mirror option in RAL? Basically all it does is just keep a track of the DUT register variables. What exactly is the function of mirror and why do we need it

Thanks in advance.