In reply to xavier.correcher:
I was telling about write->mirror scenario in the previous thread.
I would like to tell about write->read scenario so that debugging could be easier.
The register that I work upon has “RW” as the access mode.
The following is the body task of my sequence.
task body();
uvm_reg_data_t value;
uvm_reg_status_e status;
reg_model.clock_addend.write(status,'h12341234,.parent(this));
#100;
reg_model.clock_addend.read(status,value,.parent(this));
$display("RAL read value = %x",value);
endtask
Upon execution I got the following output:
RAL read value = 0000000000000000
The following are my observations from the waveform.
1.The DUT register has been written correctly via a write cycle.
2.A read operation has been initiated and the correct data is available on the read_bus.
3.Also I gave some print statements in the adapter to ensure if the read transaction has been captured and I get the correct read value being printed.
On the otherhand, when I do a read again (ie two reads after a write) the correct value is getting printed. ie RAL read value = 0000000012341234
In such a case, what could be the possible reason for the read data for not going inside the variable “value” of read task during the first call even though the read data is available in the read bus of the DUT soon afte its first call.
// The post was updated as :
I would also like to add that subsequent writes and reads give the correct value.
That is, this problem occurs only for the first read. If I write a different value to the register and read it, the correct value is updated.