In reply to chr_sue:
In reply to naveen-y:
set changes the desired value.
update writes the desired value to the DUT if desired value != mirrored value.
hi,
Thank you for replying. I have connected monitor(with analysis port) to the predictor(bus-in, implementation port in predictor) and I have done the set_auto_predict(1), in the ‘env’, which updates the mirrored_values automatically. And I have not used any ‘set’ and ‘update’ methods any where.
And one more doubt I have is that, I am getting the desired and mirrored values of different registers at different times. For example, if am getting the
desired value of ‘ctrl’ reg at time t, i get
mirrored value of ‘ctrl’ reg at time t+20 and
desired value of ‘div’ reg at time t+20, i get
mirrored value of ‘div’ reg at time t+40 and so on for the other registers(in the order in which I have written in sequence by using ‘write’ and ‘read’ register access methods).
Is it correct if we get the values of all the registers at different times?
And is it correct if we get the desired and mirrored values at different times?
Is it compulsory that we should get all the values at the same time?