Minimum number of RW required

SystemVerilog
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3

Hi Nikhil,

Thanks for the reply. If i brief on your solution, “,minimum” number of WR required to identify the faulty 2 bits in case of address bits swapped is 256?

Lets say if we have 2 more faulty bit in address bus(total 4), what will be the minimum WR required.

How it differs when Wdata and Rdata bus got this faulty 2 bits?

Regards,
Rex