In reply to Wanglj:
Yes, you can control the clock directly at the instance level from do file that is passed to the vsim command (ex: vsim top -do dofile.do)
force top.dut.i1.a1.clk = 1’b0 -time “”
(I don’t remember the exact syntax though. And I assume you are using Questasim.)
You can use the verilog force/release as well to achieve the same from your TB.