Method Overriding

SystemVerilog
, ,
7

In reply to harsh pandya:

Yeah you are right. Method overloading is not present in SV. Its a concept in OOPs initially used in C++ as I know.

For method overriding, we don’t have to declare the method as virtual.

As per my understanding method overriding happens when we declare a method in derived class with same signature. That time the method call will implement the derived class method definition instead of base class one.

I attach a method overriding code here for reference

class base;
virtual function void display();
	$display("Base");
endfunction :display
endclass :base

class derived extends base;
function void display();
	$display("Derived");
endfunction :display
endclass :derived

module tb;
	base b1;
	derived d1;
	
	initial begin
		b1=new();
		d1=new();
		//Display of base
		b1.display();
		//Display of derived
		d1.display();		
	end
endmodule :tb