In reply to run2prem:
Method overloading is the practice of declaring the same method with different signatures. The same method name will be used with different data type . This is Not Supported by SystemVerilog as of 2008
In reply to run2prem:
Method overloading is the practice of declaring the same method with different signatures. The same method name will be used with different data type . This is Not Supported by SystemVerilog as of 2008