Meaning of `ifdef SYNTHESIS

I have seen many testbench codes with



`ifndef SYNTHESIS 

What is this for?

In reply to vk7715:

This is typically used to mark areas of code that are behavioral in nature and non-synthesizable, often when the testbench will be used both emulation and simulation.

A better approach to eliminate the need for additional +define+ arguments is to use synthesis pragmas (translate_off, translate_on) which most synthesis tools use to recognize non-synthesizable code.

In reply to cgales:

“areas of code that are behavioral” – apologies if this seems like a novice question, but do these “areas of code” a part of the design (RTL) code? I am assuming it is, but I am confused as to why there would be non synthesizable code in a design

In reply to vk7715:

Your question was asking about testbench code which may be used in both simulation and emulation, and this may require annotating some testbench code as non-synthesizable.

All design code (RTL) is required to be synthesizable, but you will sometimes see designers add additional non-synthesizable code (assertions, functions to allow memory loading, etc.) into RTL code which would require these annotations. This behavioral code is just for simulation and not part of the actual design.