In reply to abasili:
Ok, now I would like to hide myself under a pile of bison poop!
While I was writing the above post I’ve copied bits and pieces of my code, as well as the code from the UVM User Guide. Well… while the code from the User Guide was correct, my real code, that I thought was a very close copy of that, was fundamentally wrong!
virtual function void connect_phase(uvm_phase phase);
ral.default_map.set_sequencer(sub_env.apb.sqr,null); // <------- Argghhhh!!!!
reg2apb_seq = reg2apb_seq_t::type_id::create("reg2apb_seq"); // we create the translation sequence
// ...
sub_env.apb.mon.item_collected_port.connect(reg_predictor.bus_in);
endfunction: connect_phase
So essentially my address_map, instead of ‘sending’ the uvm_reg_item to the reg sequencer, it was sending it to the bus sequencer, which didn’t make any sense!
I must say that going through the UVM base code, step by step, taught me a lot of things, but it has been quite a frustrating experience!
For those of you who’ve stuck all along, I owe you an apology and a thank you for the effort to read through my rant (can’t define it otherwise).
Over and out,
- Al