In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks a lot for the example. I’m clear now.
But for the 2nd question, yes, I know they’re different, in fact that’s why I used local variables. Since tag1 and tag2 may vary from 1 to 7, my intent is to cover 7 different scenarios:
(a ##1 (b && tag1==1)[->1] ##1 (c && tag2==1)[->1]) |-> d;
(a ##1 (b && tag1==2)[->1] ##1 (c && tag2==2)[->1]) |-> d;
(a ##1 (b && tag1==3)[->1] ##1 (c && tag2==3)[->1]) |-> d;
…
(a ##1 (b && tag1==7)[->1] ##1 (c && tag2==7)[->1]) |-> d;
I tried to use only one assertion to cover all these 7 scenarios, that’s why I tried to use local variable to capture the tag infromation. For now, since local variable does not work as expected, I have to use “generate” to generate 7 assertions.